1. Field of the Invention
The invention is related to the field of packet communications, and in particular, to packet processing circuitry.
2. Statement of the Problem
A communication packet is a unit of information that is transferred from one point to another over a communication system. The packet includes a header that indicates to the communication system how the packet should be processed. The primary task when processing a packet is properly routing the packet from the sender to the receiver, although there are many other tasks, such as security, service classification, billing, and address translation. Two common examples of packet communication protocols are the Internet Protocol (IP) and the Asynchronous Transfer Mode (ATM) protocol.
Communication packet processors are integrated circuits that receive, process, and transmit packets. With an insatiable demand for high-speed communications, packet processors are being driven to handle more packets at higher speeds. Compounding the problem is the desire that packet processors offer a more robust set of packet handling options.
To accomplish this difficult task, a packet processor includes a high-speed core processor that executes a packet processing software application. Under software control, the core processor processes the header of an incoming packet to retrieve context information from a memory for the packet. The context information specifies how the packet should be handled with respect to routing, security, and other areas. Under software control, the core processor then processes the context information to control packet handling.
To retrieve the desired context information, the core processor must associate the packet header with the memory locations that hold the desired context information. The core processor must then retrieve the desired context information from the associated memory locations. If the core processor modifies the context information, it must then write the modified context information back to the correct memory locations. This process is repeated for each packet, so the core processor is repeatedly associating headers with memory locations, retrieving context information, and writing modified context information to the memory locations.
This task is further complicated by the increase in processing options that can be applied to a packet. As the processing options increase, so does the size of the context information that specifies these options. The core processor must now handle increasingly larger amounts of context information, or the core processor must selectively retrieve only the desired data contained in the context information.
With increasing speeds and processing requirements, the core processor is becoming over-tasked. The result is either a loss of speed or processing options. One solution is simply to add higher-speed processors. Unfortunately, this solution adds too much cost to the underlying system.
A Content-Addressable Memory (CAM) is an integrated circuit that can search a list at high speed to provide a corresponding result. The CAM is configured with a list of selector entries. Each selector entry has a corresponding result. When the CAM receives an input selector, it searches the list of selector entries for a match. The search is accomplished at high speed by concurrently comparing each selector entry to the input selector. Unfortunately, CAMs have not been effectively applied to help solve the above problem.
The invention helps solve the above problems with a CAM that helps relieve the core processor of the complexity of retrieving selected context information. In response to a selector from packet processing circuitry, the CAM provides results that point to desired context information in memory. Advantageously, the CAM can generate additional selectors from the initial selector, so there is a reduction in use of the data bus that carries selectors to the CAM. The data bus can then be used to transfer results to the packet processing circuitry. If desired, the results bus and its associated pins can be eliminated. The CAM can operate at high speeds, and core processor capacity is freed up for other processing tasks. In addition, the context information can be managed as a single data base of context structures that is shared by the packets.
In some examples of the invention, the CAM is comprised of processing logic and selector logic. The processing logic receives a first selector including packet header information from the packet processing circuitry. The processing logic transfers the first selector to the selector logic. The processing logic generates additional selectors and transfers the additional selectors to the selector logic. The selector logic receives and processes selectors for matches and provides results corresponding to the matches. The processing logic receives the results from the selector logic and transfers at least some of the results that point to packet processing context structures to the packet processing circuitry. The CAM may even not include pins for a results bus.
The processing logic may receive the first one of the selectors over a bi-directional data bus and transfer the results over the bi-directional data bus. The processing logic may generate the additional selectors by incrementing a portion of the first selector. The processing logic may receive a search series from the packet processing circuitry and generate the additional selectors based on the search series. The processing logic may generate the additional selectors based on a search series indicated by a first result corresponding to the first selectors. The first result corresponding to the first selector may indicate an instruction for the packet processing circuitry. The first result corresponding to the first selector may indicate a trigger. The context structures may relate to network address translation, billing, packet forwarding, packet security, and packet classification. The CAM may be configured with the packet processing circuitry on a single integrated circuit.